1. Technical Field
Various embodiments of the present invention relate to a semiconductor memory apparatus. In particular, certain embodiments relate to a semiconductor memory apparatus which is capable of setting its operation mode with a reduced number of bonding pads.
2. Related Art
As the operation speed and the processing capacity of a semiconductor memory apparatus increase, the semiconductor memory apparatus begin to be equipped with a plurality of pads and a plurality of data input/output lines to input and output a plurality of data at a time. X4, X8 and X16 input/output modes are used depending upon how many data bits a semiconductor memory apparatus can simultaneously process per one read or write operation. The X4 input/output mode may mean a mode in which four data bits are simultaneously inputted or outputted per one read or write operation, and the X8 and X16 input/output modes may mean modes in which eight and sixteen data bits are simultaneously inputted or outputted per one read or write operation.
In order to improve the productivity of intact products, a wafer burn-in test is generally performed during a fabrication process of a semiconductor memory apparatus. The wafer burn-in test may mean a test in which a stress is constantly applied while the semiconductor memory apparatus is on a wafer before being packaged so normality or abnormality of the semiconductor memory apparatus is inspected. The wafer burn-in test is performed separate from a regular operation of the semiconductor memory apparatus. Therefore, the semiconductor memory apparatus includes a configuration capable of designating an input/output mode and a wafer burn-in test mode.
FIG. 1 is a diagram schematically illustrating the configuration of a related-art semiconductor memory apparatus. As shown in FIG. 1, the semiconductor memory apparatus may include a first bonding pad 10, a second bonding pad 20, and a decoding unit 30. The first bonding pad 10 receives a first bonding signal PADX4, and the second bonding pad 20 receives a second bonding signal PADX8. The decoding unit 30 is configured to receive the first and second bonding signals PADX4 and PADX8 from the first and second bonding pads 10 and 20 and decode the first and second bonding signals PADX4 and PADX8. Four decoding signals may be generated based on various combinations of logic levels of the first and second bonding signals PADX4 and PADX8. The four decoding signals may be used as signals X4, X8, X16 and WBI which respectively designate an X4 input/output mode, an X8 input/output mode, an X16 input/output mode, and a wafer burn-in test mode.
Therefore, in order to designate the X4, X8 and X16 input/output modes and the wafer burn-in test mode in the conventional semiconductor memory apparatus, it is necessary to receive signals from at least two bonding pads. Also, even in a semiconductor memory apparatus in which the X4 input/output mode is not used, two signals should be received from at least two bonding pads to designate different three operation modes.